How many registers does an x86-64 CPU have? ENOSUCHBLOG Programming, philosophy, pedaling. Home Tags Series Favorites Archive Main Site TILs How many registers does an x86-64 CPU have? Nov 30, 2020 Tags: programming , x86 This post is at least a year old. x86 is back in the general programmer discourse, in part thanks to Apple’s M1 and Rosetta 2 . As such, I figured I’d do yet another x86-64 post. Just like the last one , I’m going to cover a facet of the x86-64 ISA that sets it apart as unusually complex among modern ISAs: the number and diversity of registers available. Like instruction counting , register counting on x86-64 is subject to debates over methodology. In particular, for this blog post, I’m going to lay the following ground rules: I will count sub-registers (e.g., EAX for RAX ) as distinct registers. My justification: they have different instruction encodings, and both Intel and AMD optimize/pessimize particular sub-register use patterns in their microcode. I will count registers that are present on x86-64 CPUs, but that can’t be used in long mode. I won’t count registers that are only present on older x86 CPUs, like the 80386 and 80486 test registers . I won’t count microarchitectural implementation details, like shadow registers. I will count registers that aren’t directly addressable, like MSRs that can only be accessed through RDMSR . However, I won’t (or will try not to) double-count registers that have multiple access mechanisms (like RDMSR and RDTSC ). I won’t count model-specific registers that fall into these categories: MSRs that are only present on niche x86 vendors (Cyrix, Via) MSRs that aren’t widely available on recent-ish x86-64 CPUs Errata : I accidentally included AVX-512 in some of the original counts below, not realizing that it hadn’t been released on any AMD CPUs. The post has been updated. MSRs that are completely undocumented (both officially and unofficially) In addition to the rules above, I’m going to use the following considerations and methodology for grouping registers together: Many sources, both official and unofficial, use “model-specific register” as an umbrella term for any non-core or non-feature-set register supplied by an x86-64 CPU. Whenever possible, I’ll try to avoid this in favor of more specific categories. Both Intel and AMD provide synonyms for registers (e.g. CR8 as the “task priority register,” or TPR ). Whenever possible, I’ll try to use the more generic/category conforming name (like CR8 in the case above). In general, the individual cores of a multicore processor have independent register states. Whenever this isn’t the case, I’ll make an effort to document it. General-purpose registers The general-purpose registers (or GPRs) are the primary registers in the x86-64 register model. As their name implies, they are the only registers that are general purpose : each has a set of conventional uses 1 , but programmers are generally free to ignore those conventions and use them as they pleas

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